1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device that operates in synchronization with a clock signal. More particularly, the present invention relates to a structure to improve the internal data transfer rate of a logic-merged DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
In a semiconductor integrated circuit device in which a logic and a memory are formed on the same chip, the data bus width between the logic and the memory can be increased without restriction of the number and pitch of pin terminals. Increase of the data bus width between the logic and the memory allows more data bits to be transferred at one time. The data transfer rate can be improved significantly than the case where a discrete memory is used.
FIG. 33 schematically shows a structure of a conventional logic-merged DRAM. Referring to FIG. 33, the DRAM includes memory cell sub arrays MB#0-MB#m having a plurality of memory cells arranged in rows and columns, and sense amplifier bands SA#0-SA#n provided corresponding to memory cell sub arrays MB#0-MB#m. In each of memory cell sub arrays MB#0-MB#m, a word line WL is arranged corresponding to a memory cell row. A bit line pair is arranged corresponding to a memory cell column. In FIG. 33, one bit line pair BLP, word line WL, and a memory cell MC arranged at the crossing thereof in memory cell sub array MB#0 are shown representatively.
Sense amplifier bands SA#0-SA#n each include sense amplifier circuits provided corresponding to columns of corresponding memory cell sub arrays, and column select gates provided corresponding to respective sense amplifier circuits. A sense amplifier band (SA#1, . . . ) arranged between the memory cell sub arrays are shared by adjacent memory cell sub arrays.
The DRAM further includes row decoders RD#0-RD#m provided corresponding to memory cell sub arrays MB#0-MB#m, respectively, to drive a word line corresponding to an addressed row to a selected state, column decoders CD#0-CD#n provided corresponding to sense amplifier bands SA#0-SA#, respectively to generate a column select signal selecting a sense amplifier circuit provided corresponding to an addressed column according to a column address signal, and internal data line pairs IOPs arranged extending in the column direction common to memory cell sub arrays MB#0-MB#m to transfer data with a sense amplifier circuit provided corresponding to selected columns. Internal data line pair IOP includes complementary data lines, and is arranged along a column direction extending over memory cell sub arrays MB#0-MB#m.
Internal data line pair IOP is coupled to a read/write circuit W/P. Read/write circuit W/P is coupled to an input/output circuit QDB that inputs/outputs data with respect to a logic circuit not shown.
As shown in FIG. 33, the internal data bus width can be increased by arranging internal data line pairs IOP along the column direction over memory cell sub arrays MB#0-MB#m. Therefore, the number of data bits transferred at one time can be increased.
FIG. 34 schematically shows a structure of the memory cell sub array and sense amplifier band. Referring to FIG. 34, memory cell sub array MB# includes word lines WL arranged corresponding to rows of memory cells MC, each word line connected to a corresponding row of memory cells MC, and a plurality of bit line pairs BLP arranged corresponding to columns of memory cells MC, each bit line pair connected to a corresponding column of memory cells. Bit line pair BLP includes complementary bit lines BL and /BL. Memory cell MC is arranged corresponding to the crossing of one of bit lines BL and/BL and a word line WL. In FIG. 34, a memory cell MC arranged corresponding to the crossing of bit line BL and word line WL is shown.
Sense amplifier band SA# includes a sense amplifier circuit SA provided corresponding to a bit line pair BLP, and a column select gate CG arranged corresponding to sense amplifier circuit SA and rendered conductive according to a column select signal CSL from a corresponding column decoder. In sense amplifier band SA#, four sense amplifier circuits SA#0-SA3 form one sense amplifier group SAG. In FIG. 34, three sense amplifier groups SAG0-SAG2 are shown. A column specific signal on column select lines CSL0-CSL3 is applied to column select gates CG0-CG3 provided corresponding to the four sense amplifier circuits SA0-SA3, respectively.
In the arrangement shown in FIG. 34, one sense amplifier circuit (column) is selected in respective sense amplifier group SAG0-SAG2, . . .
Internal data line pair IOP is arranged corresponding to sense amplifier groups SAG0-SAG2, . . . , respectively. Internal data line pair IOP includes complementary data lines I/O and I/O to transfer complementary data. Internal data lines I/O0, /I/O0-I/O2, /I/O2 are arranged corresponding to sense amplifier groups SAG0-SAG2, respectively. A selected sense amplifier circuit is connected to a corresponding pair of internal data lines I/O, /I/O.
In the arrangement shown in FIG. 34, the column select is 1-out-of-4 selection. 1/4 of memory cells are selected out of one row of memory cells. For example, since there are 512 sense amplifier circuits SA in the case where 512 bits of memory cells MC are arranged in one row, 128 internal data line pairs IOP are provided. Thus, 128 sense amplifier circuits (memory cell) are selected simultaneously and connected to corresponding internal data line pairs IOP according to column select lines CSL0-CSL3, so that memory cell data of 128 bits can be transferred at a time. In the shared sense amplifier structure, sense amplifiers are arranged at both sides of memory cell block MB# in the column direction. The number of sense amplifier circuits in one sense amplifier band is 64, and the sense amplifier bands at both sides of a selected memory cell block are activated simultaneously.
The data on internal data line pair IOP is coupled to read/write circuit W/P of FIG. 33. In a data readout operation, the data held in sense amplifier circuits SAi (i=0-3) on the selected columns are transferred in parallel to preamplifiers in read/write circuit W/P of FIG. 33 via internal data line pairs IOP. Then, the data are transferred to the logic circuit via input/output circuit QDB at a predetermined sequence in synchronization with a clock signal. In data transfer from input/output circuit QDB, the number of internal transfer bits is adjusted according to the data bus width between the logic circuit and the DRAM. Data of a bit width equal to the number of memory cells in one row can be transferred simultaneously at maximum.
FIG. 35 schematically shows an interconnection layer of a memory array portion. In FIG. 35, bit line BL (/BL) is formed of refractory metal such as tungsten or refractory metal silicide. Above bit line BL (/BL), column select line CSL and word line WL are formed of a first level aluminum interconnection (1Al) lines parallel to each other. Above column select line CSL and word line WL, internal data line I/O (/I/O) is formed of a second level aluminum interconnection (2Al) line. Internal data line I/O (/I/O) is arranged parallel to bit line BL. In the case where the line capacitance of bit lines BL and /BL is increased, the noise of an adjacent bit line is overlaid by capacitive coupling to degrade the operational margin of the sense amplifier during the sense operation, i.e., when amplifying small readout voltage (memory cell data) on bit line BL or /BL. Therefore, film thickness of bit lines BL and /BL must be reduced to reduce the capacitance between the bit lines. The pitch of bit lines BL and /BL becomes smaller than that of internal data lines I/O and /I/O, and the aspect ratio of the bit lines becomes large when the film thickness becomes greater. It therefore becomes difficult to carry out the etching process on the bit lines. Since bit lines BL and /BL are located below word line WL, column select line CSL and internal data lines I/O and /I/O, increase in the film thickness of bit lines BL and /BL causes a stepped portion of the overlying interconnection layer or word line WL and column select line CSL to become greater to induce the possibility of disconnection. Taking into consideration the above factors, the film thickness of bit lines BL and /BL is made as small as possible.
Internal data lines I/O and /I/O are formed of the second level aluminum interconnection lines. The second level aluminum interconnection lines are also used as a power supply line to transmit power supply voltage Vcc and ground voltage GND and as a signal line to transmit a signal over a relatively long distance. It is therefore necessary to set the impedance as low as possible. Accordingly, the film thickness of the second level aluminum interconnection (2Al) line is made thick. The pitch of internal data lines I/O and /I/O is set greater than the bit line pitch, and one pair of internal data lines IOP is provided for four sense amplifier circuits, for example, because of the following reasons.
Since the aspect ratio is increased when the film thickness is great, it will be difficult to carry out anisotropic etching precisely to pattern internal data lines I/O and /I/O. When the etching process is not carried out properly, the edge of an interconnection line may not be etched away to cause shorting with an adjacent aluminum interconnection line that is not yet etched. In the case of a large line capacitance, noise is overlaid on a data signal during data transfer due to capacitive coupling through the line capacitance. The amplitude of the complementary data signals becomes smaller, and the operational margin of the preamplifier is degraded.
In order to avoid these problems, the pitch of internal data lines I/O and /I/O is set sufficiently greater than the bit line pitch, for example, to 4 times the bit line pitch. Therefore, the data latched in sense amplifier circuit SA cannot be transferred at one time. Thus, it was difficult to increase the band width of data transfer with the logic circuit.